This invention relates to semiconductor devices and particularly to an improved junction field effect transistor (JFET).
A conventional JFET is a three-terminal semiconductor device in which a current flowing substantially parallel to the top surface of the semiconductor chip is controlled by an externally applied vertical electric field, as shown in FIG. 1a, 1b, and 1c. It can be used as a switch or an amplifier. JFET is known as the unipolar transistor because the current is transported by carriers of one polarity, namely, the majority carriers. This is in contrast with the bipolar junction transistor, in which both majority-and-minority-carrier currents are important.
A typical n-channel JFET fabricated by the standard planar process is shown in FIG. 1. FIG. 1a depicts a JFET built in a semiconductor substrate in an epitaxial layer. FIG. 1b depicts a JFET fabricated by a double-diffused technique in a bulk semiconductor substrate. FIG. 1c is a schematic representation of both JFETs.
The active region of the JFET consists of a lightly doped n-type channel sandwiched between two heavily doped p+-gate regions. In FIG. 1a, the lower p+ region is the substrate, and the upper p+ region is formed by boron diffusion into the epitaxially grown n-type channel. The p+ regions are connected either internally or externally to form the gate terminal. Ohmic contacts attached to the two ends of the channel are known as the drain and source terminals through which the channel current flows. Alternatively, the JFET may be fabricated by the double-diffused technique with a diffused channel and an upper gate as illustrated in FIG. 1b. In both cases, the channel and the gate regions run substantially parallel the top surface of the substrate, so does the current flow in the channel.
When a JFET operates as a switch, without a gate bias voltage, the transistor has a conducting channel between the source and the drain terminals. This is the ON state. To reach the OFF state, a reverse-biasing gate voltage is applied to deplete all carriers in the channel.
The reverse voltage bias applied across the gate/channel junctions depletes free carriers from the channel and produces space-charge regions extending into the channel. With a gate voltage set between ON and OFF levels, the cross-sectional area of the channel and the channel resistance can be varied. Thus the current flow between the source and the drain is modulated by the gate voltage.
An important figure of merit of a JFET is its cutoff frequency (fco), which can be represented mathematically as follows:fco≦qa2μnNd/(4πk∈oL2),where q is the electric charge of the charge carriers, a is the channel width, μn is the mobility of the charge carriers, Nd is the doping concentration in the channel, k and ∈o are the dielectric constant and the electrical permittivity of the semiconductor material and the free space respectively, and L is the channel length.
Another important figure of merit of a JFET is the noise figure. At lower frequencies the dominant noise source in a transistor is due to the interaction of the current flow and the surface region that gives rise to the 1/f noise spectrum.
This invention provides a JFET device that has superior fco and 1/f performance over conventional JFETs and a process of making the device.